ff:acaces:12 (In proceedings)
|
Author(s) | Fabio Tordini, Marco Aldinucci and Massimo Torquati |
Title | « High-level lock-less programming for multicore » |
In | Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) -- Poster Abstracts |
Year | 2012 |
Publisher | HiPEAC |
Address | Fiuggi, Italy |
ISBN number | 9789038219875 |
URL | http://calvados.di.unipi.it/storage/paper_files/2012_ACACES_ex-abstract.pdf |
Abstract & Keywords |
Modern computers are built upon multi-core architectures. Achieving peak performance on these architectures is hard and may require a substantial programming effort. The synchronisation of many processes racing to access a common resource (the shared memory) has been a fundamental problem on parallel computing for years, and many solutions have been proposed to address this issue. Non-blocking synchronisation and transactional primitives have been envisioned as a way to reduce memory wall problem. Despite sometimes effective (and exhibiting a great momentum in the research community), they are only one facet of the problem, as their exploitation still requires non-trivial programming skills. With non-blocking philosophy in mind, we propose high-level programming patterns that will relieve the programmer from worrying about low-level details such as synchronisation of racing processes as well as those fine tunings needed to improve the overall performance, like proper (distributed) dynamic memory allocation and effective exploitation of the memory hierarchy.
Keywords: fastflow
|
@inproceedings{ff:acaces:12,
author = {Fabio Tordini and Marco Aldinucci and Massimo Torquati},
keywords = {fastflow},
booktitle = {Advanced Computer Architecture and Compilation for
High-Performance and Embedded Systems (ACACES) -- Poster
Abstracts},
url = {http://calvados.di.unipi.it/storage/paper_files/2012_ACACES_ex-abstract.pdf},
abstract = {Modern computers are built upon multi-core architectures.
Achieving peak performance on these architectures is hard and may
require a substantial programming effort. The synchronisation of
many processes racing to access a common resource (the shared
memory) has been a fundamental problem on parallel computing for
years, and many solutions have been proposed to address this
issue. Non-blocking synchronisation and transactional primitives
have been envisioned as a way to reduce memory wall problem.
Despite sometimes effective (and exhibiting a great momentum in
the research community), they are only one facet of the problem,
as their exploitation still requires non-trivial programming
skills. With non-blocking philosophy in mind, we propose
high-level programming patterns that will relieve the programmer
from worrying about low-level details such as synchronisation of
racing processes as well as those fine tunings needed to improve
the overall performance, like proper (distributed) dynamic memory
allocation and effective exploitation of the memory hierarchy.},
address = {Fiuggi, Italy},
isbn = {9789038219875},
title = {High-level lock-less programming for multicore},
publisher = {HiPEAC},
year = {2012},
}
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